Upon power-on, the 65F02 grabs the complete RAM and ROM content from the host and copies it into the on-chip RAM, except for the I/O area. The only thing the FPGA board needs to know about its host is the memory map: Where does the host have memory-mapped I/O? Up to 16 different memory maps can be stored in the FPGA, and selected via a mini DIP switch. The idea is to use this as a “universal” accelerator for 6502 and 65C02-based host computers – just plug it into the CPU socket. I dubbed this the “65F02”, where the “F” might stand for FPGA or for “Fast”. Inside the FPGA, the CPU core runs at 100 MHz. I added logic inside the FPGA which can access the external 65C02 bus with the correct timing, based on whatever clock is coming in from the host system. I packaged this in a Spartan-6 FPGA (with 64 kByte on-chip RAM), on a small circuit board which is just the size of a 40-pin dual inline package, with pins matching the 65C02 pinout. In fact, the CPU core used was developed as a 6502 core by Arlet Ottens, and extended to cover the 65C02 opcodes by Ed Spittles and David Banks. The idea of implementing a CPU core inside an FPGA is not new.
COMPLETE MICROPROCESSOR LOGICWORKS 5 UPGRADE
Here’s a re-implementation of the 65C02 in an FPGA, in a pin-compatible format that lets you upgrade those old computers and games to 100 MHz clock rate! It lived on well into the 1990s in game consoles and chess computers, mostly in its updated “65C02” CMOS version. The 6502 was the CPU in my first computer (an Apple II plus), as well as many other popular home computers of the late 1970s and 80s. Jergen posts about a re-implementation of the classic 65C02 microprocessor, found in many classic computers, in an FPGA, in a pin-compatible format that lets you upgrade those old computers and games to a 100 MHz clock rate!